View ISL59448_318785.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL59448
Data Sheet March 29, 2006 FN6160.2
500MHz Triple 2:1 Gain-of-2, Multiplexing Amplifier
The ISL59448 is a triple channel 2:1 multiplexer featuring integrated buffers with a fixed gain of 2, high slew-rate and excellent bandwidth for video switching. The device features a three-state output (HIZ), which allows the outputs of multiple devices to be tied together. A power-down mode (ENABLE) is included to turn off un-needed circuitry in power sensitive applications. When the ENABLE pin is pulled high, the part enters a power-down mode and consumes just 14mW. An additional feature is a latch enable function (LE) that allows independent logic control using a common logic bus.
Features
* 500MHz bandwidth * 1600 V/s slew rate * High impedance buffered inputs * Internally set gain-of-2 * High speed three-state outputs (HIZ) * Power-down mode (ENABLE) * Latch enable * 5V operation * Supply current 11mA/ch * Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER ISL59448IAZ (See Note) ISL59448IAZ-T7 (See Note) PACKAGE 24 Ld QSOP (Pb-free) 24 Ld QSOP (Pb-free) TAPE & REEL 7" PKG. DWG. # MDP0040 MDP0040
Applications
* HDTV/DTV analog inputs * Video projectors * Computer monitors * Set-top boxes * Security video * Broadcast video equipment
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59448 S0 0 1 X X X ENABLE 0 0 1 0 0 HIZ 0 0 X 1 0 LE 0 0 X X 1 OUTPUT INO (A, B, C) IN1 (A, B, C) Power-down High Z Last S0 State Preserved
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59448 Pinout
ISL59448 (24 LD QSOP) TOP VIEW
IN0A GND A IN0B NIC GND B IN0C NIC IN1A NIC 1 2 3 4 5 6 7 8 9 x2 x2 x2 24 NIC 23 LE S0 22 ENABLE 21 HIZ 20 OUTA 19 V+ AMPLIFIER BIAS 18 OUTB 17 OUTC 16 V15 NIC 14 S0 13 NIC LE HIZ ENABLE A logic high on LE will latch the last S0 state. This logic state is preserved when cycling HIZ or ENABLE functions. EN0 DECODE DL Q C IN0(A,B,C) DL Q IN1(A,B,C) C OUT
Functional Diagram (each channel)
+
EN1
IN1B 10 GND C 11 IN1C 12 LATCHED ON HIGH LE NIC = NO INTERNAL CONNECTION
2
FN6160.2 March 29, 2006
ISL59448
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL
V+ = +5V, V- = -5V, GND = 0V, TA = 25C, Vout = 2VP-P & RL = 500 to GND, CL = 0pF, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
+IS Enabled -IS Enabled
+IS Disabled -IS Disabled VOUT IOUT VOS Ib ROUT ROUT RIN ACL or AV LOGIC VIH VIL IIH IIL AC GENERAL PSRR Xtalk Off - ISO dG dP
Enabled Supply Current Enabled Supply Current Disabled Supply Current Disabled Supply Current Positive and Negative Output Swing Output Current Output Offset Voltage Input Bias Current HIZ Output Resistance Enabled Output Resistance Input Resistance Voltage Gain
No load, VIN = 0V, Enable Low No load, VIN = 0V, Enable Low No load, VIN = 0V, Enable High No load, VIN = 0V, Enable High VIN = 2.5V; RL = 500 VIN = 0.825V RL = 10
27 -32 2.3 -0.1 3.1 80 -40
31 -29 2.7
35 -25 3.3 0.1
mA mA mA mA V
3.9 180 -25 -2 900 0.2 10 -10 -1 1150
mA mV A M
VIN = 0V HIZ = Logic High HIZ = Logic Low VIN = 1.75V RL = 500
-3 700
1.94
1.98
2.035
V/V
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs) VH = 5V VL = 0V 200 -3
2 0.8 258 319 3
V V A A
Power Supply Rejection Ratio Channel to Channel Crosstalk Off-state Isolation Differential Gain Error Differential Phase Error
DC, PSRR V+ & V- combined VOUT = 0dBm f = 10MHz, ChX-Ch Y-Talk VIN = 1Vp-p; CL = 1.1pF f = 10MHz, Ch-Ch Off Isolation VIN = 1Vp-p; CL = 1.1pF NTC-7, RL = 150, CL = 1.1pF NTC-7, RL = 150, CL = 1.1pF
52
72 88 72 0.015 0.015
dB dB dB %
3
FN6160.2 March 29, 2006
ISL59448
Electrical Specifications
PARAMETER BW V+ = +5V, V- = -5V, GND = 0V, TA = 25C, Vout = 2VP-P & RL = 500 to GND, CL = 0pF, unless otherwise specified. (Continued) DESCRIPTION Small Signal -3dB Bandwidth Large Signal -3dB Bandwidth Small Signal -3dB Bandwidth Large Signal -3dB Bandwidth FBW 0.1dB Bandwidth 0.1dB Bandwidth SR Slew Rate CONDITIONS VOUT = 0.2Vp-p; RL = 500, CL = 1.1pF VOUT = 2Vp-p; RL = 500, CL = 1.1pF VOUT = 0.2Vp-p; RL = 150, CL = 1.1pF VOUT = 2Vp-p; RL = 150, CL = 1.1pF VOUT = 2Vp-p; RL = 500, CL = 1.1pF VOUT = 2Vp-p; RL = 150, CL = 1.1pF 25% to 75%, RL = 150, Input Enabled, CL = 1.1pF MIN TYP 570 280 510 260 140 60 1600 MAX UNIT MHz MHz MHz MHz MHz MHz V/s
TRANSIENT RESPONSE tr, tf Large Signal tr, tf, Small Signal
ts 0.1%
Large Signal Rise, Fall TImes, tr, tf, 10% - 90% Small Signal Rise, Fall TImes, tr, tf, 10% - 90% Settling TIme 0.1%
VOUT = 2Vp-p; RL = 500, CL = 1.1pF VOUT = 2Vp-p; RL = 150, CL = 1.1pF VOUT = 0.2Vp-p; RL = 500, CL = 1.1pF VOUT = 0.2Vp-p; RL = 150, CL = 1.1pF VOUT = 2Vp-p; RL = 500, CL = 1.1pF VOUT = 2Vp-p; RL = 150, CL = 1.1pF
1.2 1.3 0.7 0.85 5 4.5 2 2.5
ns ns ns ns ns ns ns ns
ts 1%
Settling TIme 1%
VOUT = 2Vp-p; RL = 500, CL = 1.1pF VOUT = 2Vp-p; RL = 150, CL = 1.1pF
SWITCHING CHARACTERISTICS VGLITCH Channel -to-Channel Switching Glitch Enable Switching Glitch HIZ Switching Glitch tSW-L-H tSW-H-L tpd tLH Channel Switching Time Low to High Channel Switching Time High to Low Propagation Delay Latch Enable Hold time VIN = 0V, CL = 1.1pF VIN = 0V CL = 1.1pF VIN = 0V CL = 1.1pF 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% to 10% LE = 0 40 250 200 18 20 0.9 10 mVP-P mVP-P mVP-P ns ns ns ns
4
FN6160.2 March 29, 2006
ISL59448 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 1 10 FREQUENCY (MHz) 100 1k CL INCLUDES 0.6pF BOARD CAPACITANCE CL=3.3pF CL=2.1pF CL=0.6pF Vout=0.2Vp-p CL=13.1pF NORMALIZED GAIN (dB) CL=9.3pF CL=6.7pF CL=5.1pF 10 8 6 4 2 0 -2 -4 -6 -8 -10 1 10 FREQUENCY (MHz) 100 1k CL INCLUDES 0.6pF BOARD CAPACITANCE CL=5.1pF CL=0.6pF CL=9.3pF Vout=2Vp-p CL=13.1pF
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD
FIGURE 2. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD
2 1 0 NORMALIZED GAIN (dB)
Vout=0.2Vp-p CL=1.1pF
RL=1k RL=500
0.2 0.1 0 NORMALIZED GAIN (dB)
Vout=0.2Vp-p CL=1.1pF
RL=150
-1 -2 -3 -4 -5 -6 -7 -8 1 10
RL=150 RL=250
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 RL=500
100
1k
-0.8
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 3. GAIN vs FREQUENCY vs RL
100 VSOURCE=2Vp-p OUTPUT IMPEDANCE () OUTPUT IMPEDANCE () 10k
FIGURE 4. 0.1dB GAIN FLATNESS
VSOURCE=2Vp-p
10
1000
1
100
0.1 0.1
1
10 FREQUENCY (MHz)
100
1k
10 0.1
1
10 FREQUENCY (MHz)
100
1k
FIGURE 5. ZOUT vs FREQUENCY - ENABLED
FIGURE 6. ZOUT vs FREQUENCY - HIZ
5
FN6160.2 March 29, 2006
ISL59448 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
1M VSOURCE ==2Vp-p SOURCE 2Vp-p 100k INPUT IMPEDANCE () 10k (dB) 1k 100 10 1 0.3 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 1 10 100 FREQUENCY (MHz) 1k -100 0.1 1 10 FREQUENCY (MHz) 100 1k OFF ISOLATION INPUT X TO OUTPUT X VIN=1Vp-p INPUT X TO OUTPUT Y CROSSTALK
(Continued)
FIGURE 7. ZIN vs FREQUENCY
0 VSOURCE=1Vp-p -10 -20 PSRR (dB) -30 -40 -50 -60 -70 0.3 PSRR (V-) VOLTAGE NOISE (nV/Hz) 50
FIGURE 8. CROSSTALK AND OFF-ISOLATION
60
40
30
PSRR (V+)
20
10
1
10 FREQUENCY (MHz)
100
1k
0 100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 9. PSRR
FIGURE 10. INPUT NOISE vs FREQUENCY
VOUT=0.2Vp-p 0.2 RL=500 CL=1.1pF OUTPUT VOLTAGE (V) 0.2
VOUT=0.2Vp-p RL=150 CL=1.1pF
OUTPUT VOLTAGE (V)
0.1
0.1
0
0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 11. SMALL SIGNAL TRANSIENT RESPONSE; RL=500
FIGURE 12. SMALL SIGNAL TRANSIENT RESPONSE; RL=150
6
FN6160.2 March 29, 2006
ISL59448 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
VOUT=2Vp-p 2.0 OUTPUT VOLTAGE (V) RL=500 CL=1.1pF OUTPUT VOLTAGE (V) 2.0
(Continued)
VOUT=2Vp-p RL=150 CL=1.1pF
1.0
1.0
0
0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 13. LARGE SIGLNAL TRANSIENT RESPONSE; RL=500
50 INPUT RISE, FALL TIMES < 200ps 40 OVERSHOOT (%) VOUT=2Vp-p
FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE; RL=150
50 INPUT RISE, FALL TIMES < 200ps 40 OVERSHOOT (%) VOUT=2Vp-p
VOUT=1.4Vp-p VOUT=1Vp-p
VOUT=1.4Vp-p VOUT=1Vp-p
30
VOUT=0.2Vp-p
30
VOUT=0.2Vp-p
20
20
10
10
0
2
4
CL (Pf)
6
8
10
0
2
4
CL (Pf)
6
8
10
FIGURE 15. POSITIVE PULSE OVERSHOOT vs VOUT, CL; RL=500
50 INPUT RISE, FALL TIMES < 200ps 40 OVERSHOOT (%) VOUT=1.4Vp-p 30 VOUT=2Vp-p
FIGURE 16. POSITIVE PULSE OVERSHOOT vs VOUT, CL; RL=150
50 INPUT RISE, FALL TIMES < 200ps VOUT=2Vp-p VOUT=1.4Vp-p
40 OVERSHOOT (%) VOUT=1Vp-p
30 VOUT=1Vp-p
20
20
10 VOUT=0.2Vp-p 0 2 4 6 8 10
10 VOUT=0.2Vp-p 0 2 4 CL (Pf) 6 8 10
CL (pF)
FIGURE 17. NEGATIVE PULSE OVERSHOOT vs VOUT, CL; RL=500
FIGURE 18. NEGATIVEPULSE OVERSHOOT vs VOUT, CL; RL=150
7
FN6160.2 March 29, 2006
ISL59448 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
(Continued)
1V/DIV
1V/DIV
S0, S1 50 TERM.
VIN=0V
S0, S1 50 TERM.
VIN=1V
0 20mV/DIV
0
0 VOUT A, B, C 20ns/DIV
1V/DIV
0
VOUT A, B, C 20ns/DIV
FIGURE 19. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
FIGURE 20. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V
ENABLE 50 TERM. 1V/DIV
VIN=0V
ENABLE 50 TERM. 1V/DIV
VIN=1V
0 100mV/DIV VOUT A, B, C 0 20ns/DIV
0
2V/DIV
0
VOUT A, B, C 20ns/DIV
FIGURE 21. ENABLE SWITCHING GLITCH VIN = 0V
FIGURE 22. ENABLE TRANSIENT RESPONSE VIN = 1V
HIZ 50 TERM. 1V/DIV
VIN=0V
HIZ 50 TERM. 1V/DIV
VIN=1V
0 200mv/DIV
0
0 VOUT A, B, C 10ns/DIV
2V/DIV
VOUT A, B, C 0 10ns/DIV
FIGURE 23. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 24. HIZ TRANSIENT RESPONSE VIN = 1V
8
FN6160.2 March 29, 2006
ISL59448 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 1.2 1.136W QSOP24 JA=88C/W POWER DISSIPATION (W) 1 0.8 0.6 0.4 0.2 0 QSOP24 JA=115C/W 870mW
(Continued)
1.2 POWER DISSIPATION (W) 1 0.8 0.6 0.4 0.2 0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
9
FN6160.2 March 29, 2006
ISL59448 Pin Descriptions
ISL59448 (24 LD QSOP) 8 4, 7, 9, 13, 15, 24 10 12 5 11 14 17 18 16 20 19 22 PIN NAME IN1A NIC IN1B IN1C GNDB GNDC S0 OUTC OUTB VOUTA V+ ENABLE Circuit 1 Circuit 1 Circuit 4 Circuit 4 Circuit 2 Circuit 3 Circuit 3 Circuit 4 Circuit 3 Circuit 4 Circuit 2 EQUIVALENT CIRCUIT Circuit 1 DESCRIPTION Channel 1 input for output amplifier "A" Not Internally Connected; it is recommended these pins be tied to ground to minimize crosstalk. Channel 1 input for output amplifier "B" Channel 1 input for output amplifier "C" Ground pin for output amplifier "B" Ground pin for output amplifier "C" Channel selection pin. LSB (binary logic code) Output of amplifier "C" Output of amplifier "B" Negative power supply Output of amplifier "A" Positive power supply Device enable (active low) w/Internal pull-down resistor. A logic High puts device into power-down mode with the only logic circuitry active. All logic states are preserved post power-down. This state is not recommended for logic control where more than one MUXamp share the same video output line. Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1) logic state. HIZ and ENABLE functions are not latched with the LE pin. Output disable (active high) w/internal pull-down resistor. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. Channel 0 for output amplifier "C" Channel 0 for output amplifier "B" Channel 0 for output amplifier "A" Ground pin for output amplifier "A"
23 21
LE HIZ
Circuit 2 Circuit 2
6 3 1 2
IN0C IN0B IN0A GNDA
Circuit 1 Circuit 1 Circuit 1 Circuit 4
10
FN6160.2 March 29, 2006
ISL59448 AC Test Circuits
ISL59448 VIN 50 or 75 *CL 1.1pF RL 500, or 150 LCRIT VOUT
Application Information
General
Key features of the ISL59448 include a fixed gain of 2, buffered high impedance analog inputs and excellent AC performance at output loads down to 150 for video cabledriving. The current feedback output amplifiers are stable operating into capacitive loads. For the best isolation and crosstalk rejection, all GND pins and NIC pins must connect to the GND plane.
*CL Includes PCB trace capacitance FIGURE 27A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59448 LCRIT VIN 50 or 75 CL RS CS RL 500, or 75
AC Design Considerations
High speed current-feed amplifiers are sensitive to capacitance at the inverting input and output terminals. The ISL59448 has an internally set gain of 2, so the inverting input is not accessible. Capacitance at the output terminal increases gain peaking (Figure 1) and pulse overshoot (Figures15 thru 18). The AC response of the ISL59448 is optimized for a total capacitance of 1.1pF over the load range of 150 to 500. PC board trace length should be kept to a minimum in order to minimize output capacitance and prevent the need for controlled impedance lines. At 500MHz trace lengths approaching 1" begin exhibiting transmission line behavior and may cause excessive ringing if controlled impedance traces are not used. Figure 27A shows the optimum interstage circuit when the total output trace length is less than the critical length of the highest signal frequency. For applications where pulse response is critical and where inter-stage distances exceed LCRIT, the circuit shown in Figure 27B is recommended. Resistor RS constrains the capacitance seen by the amplifier output to the trace capacitance from the output pin to the resistor. Therefore, RS should be placed as close to the ISL59448 output pin as possible. For inter-stage distances much greater than LCRIT, the back-loaded circuit shown in Figure 27E should be used with controlled impedance PCB lines, with RS and RL equal to the controlled impedance. For applications where inter-stage distances are long, but pulse response is not critical, capacitor CS can be added to low values of RS to form a low-pass filter to dampen pulse overshoot. This approach avoids the need for the large gain correction required by the -6dB attenuation of the backloaded controlled impedance interconnect. Load resistor RL is still required but can be 500 or greater, resulting in a much smaller attenuation factor.
FIGURE 27B. INTER-STAGE APPLICATION CIRCUIT
ISL59448 LCRIT VIN 50 TEST EQUIPMENT 56.2 50
RS
475 *CL 1.1pF
*CL Includes PCB trace capacitance FIGURE 27C. 500 TEST CIRCUIT WITH 50 LOAD
ISL59448 LCRIT VIN 50,or 75 RS 118 *CL 1.1pF 86.6 TEST EQUIPMENT 50
*CL Includes PCB trace capacitance FIGURE 27D. 150 TEST CIRCUIT WITH 50 LOAD
ISL59448 LCRIT VIN 50 or 75 RS 50 or 75 *CL 1.1pF TEST EQUIPMENT
50 or 75
*CL Includes PCB trace capacitance FIGURE 27E. BACKLOADED TEST CIRCUIT FOR 75 VIDEO CABLE APPLICATION
Control Signals
S0, S1, ENABLE, LE, HIZ - These are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three amplifiers are switched simultaneously from their respective inputs. The ENABLE, LE, HIZ pins are used to disable the part to save power, latch in the last logic state and three-state the output amplifiers, respectively. For
AC Test Circuits
Figure 27C and 27D illustrate the optimum output load for testing AC performance at 500 and 150 loads. Figure 27E illustrates the optimun output load for 50 and 75 cable-driving. 11
FN6160.2 March 29, 2006
ISL59448
control signal rise and fall times less than 10ns the use of termination resistors close to the part will minimize transients coupled to the output.
ENABLE and Power-down States
The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The Power-down state is established within approximately 200ns (Figure 22), if a logic high (>2V) is placed on the ENABLE pin. In the power-down state, the output has no leakage but has a large variable capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited powerdown output impedance.
Power-up Considerations
The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 4) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+.
LE State
The ISL59448 is equipped with a Latch Enable pin. A logic high (>2V) on the LE pin latches the last logic state. This logic state is preserved when cycling HIZ or ENABLE functions.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
HIZ State
An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 15ns (Figure 14) by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output impedance is ~1000 (Figure 6). The supply current during this state is same as the active state.
V+ SUPPLY LOGIC POWER GND SIGNAL DE-COUPLING CAPS V- SUPPLY
SCHOTTKY PROTECTION S0 GND IN0 IN1
V+
V+ LOGIC CONTROL
EXTERNAL CIRCUITS
VV+
V+ V+ OUT VV-
V-
V-
FIGURE 28. SCHOTTKY PROTECTION CIRCUIT
12
FN6160.2 March 29, 2006
ISL59448 PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip line are used. * Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible - Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
13
FN6160.2 March 29, 2006
ISL59448 QSOP Package Outline Drawing
(R)
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6160.2 March 29, 2006

▲Up To Search▲

Price & Availability of ISL59448

	To Download ISL59448 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .